Co-Packaged Silicon-Photonics Based Optical Transceivers for High-Speed Datacenter Interconnects
Hosted By: Optical Communications Technical Group
25 October 2022 12:00 - 13:00
Eastern Time (US & Canada) (UTC -05:00)Silicon photonics based optical interconnects (I/O) are being explored as a viable alternative to circumvent the reach, bandwidth and power limitations of electrical interconnects for data centers. Current high-volume products for optical data-center interconnects are in the form of pluggable modules composed of discrete electronics and photonics ICs that plug into server racks. These modules are still limited in energy efficiency due to the relatively long (inches-long) high-speed electrical interconnect between the pluggable module and the processing unit (XPU).
However, recent advances in ultra-compact silicon-based optical modulators and integrated lasers, along with a migration of the interface electronics to densely-integrated silicon processes have led to the development of compact optical I/O modules. These can be collocated on the same package as the XPU (‘co-packaged’) to reduce the length of the high-speed electrical interconnect between the XPU and the optical module to only a few centimeters resulting in advantages in energy efficiency and shoreline bandwidth density.
In this webinar hosted by the Optical Communications Technical Group, Jahnavi Sharma from Intel Labs will review prototypes of silicon-based intensity-modulated optical transceivers and recent work on scaling optical I/O data rates at iso-energy efficiency through the use of dense wavelength division multiplexing (DWDM).
Subject Matter Level: Intermediate - Assumes basic knowledge of the topic
What You Will Learn:
• An overview of Intel Lab's silicon photonics research for enabling optical I/O in datacenters
• A summary of Intel's most-recent advances in silicon photonics components for high-speed optical transceivers
• Insights on the design of the companion CMOS-based electronics for enabling ultra-high-speed co-packaged optical links
Who Should Attend:
• Researchers and engineers interested in silicon photonics for datacenter
• Researchers and engineers interested in high-speed CMOS wireline electronics
About the Presenter: Jahnavi Sharma from Intel Labs
Jahnavi Sharma is a researcher with Intel Labs, Hillsboro, OR, USA. Sharma received the dual bachelor’s and master’s degrees in electrical engineering from IIT Madras, Chennai, India, in 2009, and the M.S. and Ph.D. degrees (with a focus on CMOS signal synthesizers) in electrical engineering from Columbia University, New York, USA in 2015 and 2017 respectively. Sharma has held internship positions with IBM Yorktown Research Center in 2014, and with Bell Labs in 2013 and 2015. She was the recipient of the IBM Ph.D. Fellowship Award in 2015. Sharma’s research interests include developing integrated circuit solutions for emerging wireline and wireless applications, pushing performance through both system- and block-level innovations in CMOS and compound semiconductors.
