Held in conjunction with:
Progress continues on the design and clean room fabrication of integrated photonics, and companies have commercialized products based on integrated photonics on both the InP and silicon platforms. There is growing awareness that the chip fabrication is less of a barrier to commercialization, and attention is increasingly turning to the cost of the overall package. This cost includes the bill of materials of the package itself, the amortized cost of assembly tools, and labor. Addressing the cost requires an examination of the entire ecosystem, from the chip design and fabrication to the assembly and surrounding electronics.
There are several notable efforts going on worldwide to address various aspects of this packaging challenge. This workshop aims to complement these efforts by clarifying what is the vision of the different elements of the ecosystem. Where is the community currently headed with regard to manufacturing tools? Design software? Chip fabrication? Where will we be in 5 years?
The workshop goal will emphasize the roadmap for these critical elements, rather than to review the state of the art today. If possible, speakers and perhaps attendees will be given a draft roadmap to stimulate discussion, for possible publication.
Key questions to be addressed with respect to ICT
2016 Program Committee
- What are the key obstacles to realizing high volumes and low cost?
- What technologies offer the best solutions to reduce the cost?
- What is the role of standard packaging?
- What is the long term vision for tools, chips, packaging, and electronics?
Tom Hausken, OSA, USA, Chair
Peter O'Brien, Tyndall National Institute, Ireland, Chair
Madeleine Glick, University of Arizona, USA
Dan Kilper, University of Arizona, USA
Shayan Mookherjea, University of California, San Diego, USA
Nasser Peyghambarian, University of Arizona, USA
Ming Wu, University of California, Berkeley, USA